Table of Contents
EtherCAT timing has two clocks: the network cycle and the local application cycle. An EtherCAT slave controller can pass the first and still fail the second if the host transfer, firmware scheduling and output update do not fit the deadline.
Specify the local process data, host interface and synchronization behavior before comparing controller ICs. Include firmware and device-description work in the replacement cost.
What determines whether an ESC fits the cycle time?
The application must exchange process data, compute the next state and update the output within its assigned deadline. Network frame processing is only part of that path.
| Stage | Example budget | What to measure |
|---|---|---|
| Host transfer, 64 bytes at 20 MHz | 25.6 µs | Bus mode, commands, addresses, status checks and chip-select gaps |
| Application computation | 45 µs | Worst-case task time, interrupts and concurrent peripherals |
| Remaining before overhead | 29.4 µs | Protocol overhead, jitter and retry margin |
| Total cycle | 100 µs | End-to-end output or sampling event |
For a hypothetical 100-microsecond application cycle, assume 32 bytes of input data and 32 bytes of output data must cross a 20 MHz serial host interface. Sending those 64 bytes takes at least 64 × 8 ÷ 20,000,000 = 25.6 microseconds. Commands, addresses, status checks, chip-select gaps and software handling add to that lower bound.
If application computation takes another 45 microseconds, only 29.4 microseconds remain before protocol overhead and timing margin. A controller with a faster advertised network cycle does not fix a saturated local host path.
The LAN9252 product page identifies an EtherCAT controller with integrated Ethernet PHYs. The LAN9253 datasheet describes host-bus and SPI/SQI options, process-data memory and distributed-clock support. Those capabilities need to be matched to the specific MCU and application workload. Measure worst-case transfer and scheduling time under the full workload, including interrupts, concurrent peripherals and mailbox activity that can delay process-data handling.
A shared package is not a migration plan
LAN9252 and LAN9253 both appear in 64-pin QFN designs, which makes a board-level swap look plausible. The package only tells you that the board can physically accept the part; it says nothing about pin functions, host access or firmware.
Microchip’s EtherCAT product selection guide lists feature differences across LAN9252, LAN9253 and LAN9254. The LAN9253 datasheet also discusses operating modes and migration caveats. Use those documents to identify which items differ, then verify each against the exact silicon revision.
| Migration item | Why it can break | Evidence to obtain |
|---|---|---|
| Pins and power | The same package does not mean the same pin functions | Pin-by-pin mapping, supply domains, reset and strap requirements |
| Host access | Bus mode and timing may differ | Transaction format, bus mode, driver changes |
| Process data | Memory allocation and mapping may differ | Memory map and consistency of input/output updates |
| Synchronization | Clock configuration and event handling may differ | Clock setup, event behavior and measured output timing |
| Device identity | EEPROM, ESI and firmware identity must match | EEPROM or emulation data, ESI description and firmware identity |
| Fault behavior | Link loss, watchdog and restart behavior may differ | Link loss, watchdog action, restart and stale-data handling |
Check current errata and the ordering suffix when selecting samples. A family-level comparison cannot establish the behavior of every silicon revision or temperature grade.
How should distributed clocks be qualified?
Measure the timing of the actual output or sampling event relative to the required synchronization point. Correct clock synchronization inside the ESC is only one input to that result.
A host can receive a synchronization interrupt on time and still deliver the next output late. The data may not have been prepared, a higher-priority interrupt may intervene, or the output peripheral may update on a different boundary.
Test the longest expected process-data mapping and the intended network topology. Capture both timing offset and jitter, then repeat with the supported background communications active. Where the design uses double buffering or a hardware trigger, verify the exact instant at which new data becomes effective.
Define safe behavior for missing or stale data with the machine’s control requirements. The EtherCAT state machine, application watchdog and output hardware must agree on that behavior. A network state transition does not automatically produce the machine’s intended safe response.
What the procurement release should contain
A release package should identify the approved ESC ordering code, board revision, firmware, ESI file, host driver and test configuration. Retain the measured process-data latency and synchronization results alongside functional test results.
If an alternate misses the deadline, first determine whether the limit is the host transfer, application execution or output update. A wider host bus or changed firmware architecture may solve the problem, but it also changes the scope and cost of the replacement.
The legacy industrial Ethernet sourcing guide addresses continuity for ordinary controller designs. EtherCAT migration adds protocol-specific process-data and synchronization obligations.
For an industrial sourcing request, include cycle time, input/output byte counts, host interface, package, temperature grade and firmware constraints. For exact Microchip ordering codes, confirm the host-interface option, port configuration and silicon revision before sampling. The release package, not the controller headline, is the evidence that the migration is complete.
Frequently Asked Questions (FAQ)
Is an EtherCAT slave controller the same as an ordinary Ethernet controller?
No. An ESC handles EtherCAT-specific frame processing and process-data exchange. An ordinary Ethernet controller is not a substitute simply because both use Ethernet signaling.
Does distributed-clock support guarantee that every output changes at the intended instant?
No. The application must prepare data on time and use the synchronization event correctly. Host transfer, firmware scheduling and the output hardware remain part of the timing path.
Can an ESI file be reused unchanged with a different controller or firmware?
Only after its device identity, process-data mapping, mailbox behavior and supported modes have been checked against the new implementation. A reused file that allows startup can still misdescribe the device.
What is the difference between LAN9252 and LAN9253?
Both are EtherCAT slave controllers, but their host-interface options, process-data memory, port configuration and migration details differ. Use Microchip's selection guide to identify the differences, then verify each item against the exact datasheet and ordering suffix. A higher family number is not a drop-in guarantee.
