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Two precision digital-to-analog converters can have the same resolution while supporting different useful update rates. The serial interface may accept a new code before the analog output has settled to the accuracy the application needs. A fast headline settling specification may also use a much wider error band than the design allows.
This matters when sourcing an alternate for a programmable supply, actuator command or calibration output. Compare the voltage delivered to the load at the required observation time. Resolution is one input to that decision, not the complete specification.
How do you turn DAC resolution into a settling requirement?
Convert the output span into the voltage represented by one least significant bit, then choose the allowable dynamic error at the application’s observation time. For an ideal N-bit DAC, one LSB is approximately the full output span divided by 2ᴺ.
For a hypothetical 16-bit DAC with a 10 V span, one LSB is about 152.6 µV. A half-LSB settling window is about 76.3 µV. By comparison, 0.1% of the span is 10 mV. A device that reaches the latter window quickly has not necessarily settled to the former.
TI’s precision data-converter selection guide distinguishes settling time from update time and explains the roles of code-step size and the analog response. Retain the specified error band, start event, load and output step with every settling number in the comparison.
The dynamic window must also fit within the total output-error allocation. If reference drift and amplifier offset already consume the accuracy budget, a narrow settling result alone will not rescue the system.
Why is glitch impulse different from settling time?
Glitch impulse describes a brief disturbance during a code transition, while settling describes how long the output takes to enter and remain within a defined final-value window. An application may be sensitive to one, both or neither, depending on when and how it uses the output.
Glitch impulse is commonly expressed in volt-seconds, often nV·s. That unit describes a voltage-time integral; it is not energy in joules without an additional load model. A peak-voltage reading alone also does not reproduce the impulse figure.
The Analog Devices AD5780 data sheet specifies settling and glitch under distinct conditions. Its treatment illustrates why the output step, reference configuration and external buffer belong in the comparison rather than in discarded footnotes.
A low-pass filter can reduce a short disturbance, but adds a response-time tradeoff. Procurement should ask which filter and load were used for the quoted performance, especially when a proposed alternate needs a different external amplifier.
Build a timing budget around the observation event
Start at the event that matters to the application: a host command, a latch signal or a synchronized update. Then account for transfer time, command overhead, analog settling and the required stable interval.
As an illustrative schedule, a 24-bit transfer at 10 MHz takes 2.4 µs, before chip-select gaps or software overhead. Add an assumed 1 µs control interval and a hypothetical 12 µs analog settling requirement, and the sequential path reaches 15.4 µs. This is a constructed example, not a device specification.
Preloading a register may overlap communication with earlier activity. A simultaneous-update pin may align several channels. Neither feature automatically aligns their settled output voltages. Check the device’s actual register architecture and timing definitions before subtracting time from the budget.
Which load and reference conditions should an alternate reproduce?
Reproduce the resistive and capacitive load, output swing, reference source and temperature range that determine the delivered voltage. Test both small and large code changes, including transitions likely to stress the architecture.
Use a short qualification matrix:
| Operating case | What to observe | Why it can expose a substitution problem |
|---|---|---|
| Large positive and negative steps | Slew and final settling | Output stages may be asymmetric |
| Small steps near a critical code | Glitch and recovery | A full-scale test can miss a local disturbance |
| Maximum load capacitance | Ringing and stability | Cable or filter loading changes the response |
| Multiple channels updating | Reference disturbance and crosstalk | Shared resources may limit independence |
| Power-up and shutdown | Defined output and recovery | Reset behavior can affect connected equipment |
Measurement bandwidth, probe loading and the trigger definition must be recorded. Otherwise a difference between reports may be a difference between setups.
The procurement approval should identify the DAC, reference, output buffer, firmware timing and external network as a controlled configuration. That is the configuration the next sample and production lot must reproduce.
Frequently Asked Questions (FAQ)
Does a monotonic DAC guarantee an accurate output voltage?
No. Monotonicity describes the direction of output changes with code. Offset, gain, reference error, nonlinearity, drift and loading still affect absolute accuracy.
Can a faster SPI clock fix slow analog settling?
It can reduce transfer time, but cannot remove output slew, amplifier recovery or filter settling. Evaluate digital transfer and analog response as separate timing limits.
Should the output buffer be included in alternate qualification?
Yes. Its offset, swing, current capability, stability and settling can dominate the delivered output. An unbuffered DAC replacement cannot be assessed independently of that stage.
