Isolated Gate Driver Selection: CMTI, DESAT, and Miller Clamp

Table of Contents

• Start With the Power Switch and Topology
• Rate the Barrier for Working Voltage and Lifetime
• Match Drive Current to Gate Charge and Switching Targets
• Use CMTI as a System Requirement
• Coordinate DESAT, Miller Clamp, and UVLO
• Include Isolated Bias, Layout, and Thermal Conditions
• Qualify the Exact Driver With the Power Stage

An isolated gate driver sits between low-voltage control and a high-energy switching node. Its job is broader than transferring PWM across a barrier: it must charge and discharge the selected gate, hold the switch off during fast common-mode events, establish safe undervoltage behavior, and report or act on faults before the power stage exceeds its limits.

Selection therefore starts with the power semiconductor and converter topology. Isolation voltage and peak drive current are necessary filters, but neither proves that the driver will control switching loss, false turn-on, short-circuit energy, or lifetime on the final board.

Start With the Power Switch and Topology

Record switch technology and exact part number, maximum bus voltage, topology, switching frequency, gate charge versus operating point, recommended turn-on and turn-off voltages, threshold range, internal gate resistance, reverse-transfer capacitance, short-circuit capability if specified, and desired rise/fall times. Include parallel devices and module internal inductance.

An IGBT, silicon MOSFET, SiC MOSFET, and GaN FET can require different gate rails, output impedance, dead time, protection method, and package layout. Use the power-device data sheet and evaluation guidance rather than carrying a familiar +15 V/−5 V convention into a different technology.

Map high-side, low-side, half-bridge, full-bridge, and multilevel positions. For each driver, state its primary and secondary references, maximum switch-node slew, PWM duty range, startup state, and fault response. If one package contains two channels, verify interchannel isolation, delay matching, bootstrap or isolated-bias needs, and whether both channels can remain on or off in every intended state.

Rate the Barrier for Working Voltage and Lifetime

Isolation withstand test voltage, surge rating, working voltage, and common-mode transient immunity describe different properties. A brief production or qualification withstand test is not the continuous working-voltage rating. Select basic or reinforced isolation from the applicable system safety analysis, expected working waveform, insulation standard, pollution degree, overvoltage category, package creepage/clearance, and required lifetime.

Review the original manufacturer’s safety certificates for the exact package and orderable code. A family can include narrow- and wide-body packages with different ratings. Board creepage, slots, coating, contamination, and connector spacing must preserve the required insulation outside the IC.

Barrier lifetime depends on voltage magnitude, waveform, frequency, temperature, and the manufacturer’s insulation model. Avoid approving a device solely because its headline kilovolt number exceeds another part’s. The ADI overview of isolated gate drivers provides architecture context; the project still needs a system-specific insulation assessment.

Match Drive Current to Gate Charge and Switching Targets

Peak source/sink current is not the same as average capability or output impedance. Estimate the current required to move gate charge within the target transition, then include driver output resistance, external gate resistance, power-device internal resistance, loop inductance, and any separate turn-on/turn-off path.

A higher peak rating does not guarantee faster or cleaner switching if the loop is inductive. Excessively fast edges can increase overshoot, ringing, electromagnetic interference, and false turn-on. Slower edges reduce those effects but increase switching loss. Use gate resistors, split outputs, diodes, active gate control, or ferrite elements only with waveforms that show the resulting VGS, VDS/VCE, current, and loss.

Check propagation delay, pulse-width distortion, channel-to-channel mismatch, temperature drift, and minimum pulse width. These values enter dead-time design and volt-second balance. A typical room-temperature delay is not enough when the system must avoid shoot-through across supply and temperature extremes.

The driver also dissipates energy while charging and discharging the gate. Estimate gate-drive power from total gate charge, voltage swing, switching frequency, and channel count, then add output-stage and isolated-bias losses. Verify junction temperature in the selected package and layout.

Use CMTI as a System Requirement

Common-mode transient immunity (CMTI) is the ability to maintain correct behavior while voltage across the isolation barrier changes rapidly. In a half-bridge, switch-node dV/dt can capacitively couple through the barrier, package, bias transformer, measurement equipment, and PCB. A driver can pass a data-sheet CMTI test and still misbehave in a board with excessive parasitic coupling or supply bounce.

Define expected dV/dt from measured or modeled switching transitions, including overshoot and ringing. Compare it with the driver’s specified conditions: common-mode amplitude, temperature, supply, input state, output load, and failure criterion. Keep margin because production devices, gate resistance, bus voltage, and layout can change edge rate.

Separate CMTI from propagation delay and isolation rating. CMTI does not state how long the barrier survives its working voltage, and a high isolation withstand figure does not prove immunity to fast transients. A digital isolator can transfer logic across a barrier, but it normally does not supply the peak gate current or integrated protection expected from a gate driver.

Minimize primary-to-secondary coupling in the isolated bias supply, keep the gate loop short, control the switch-node copper, and prevent shared source inductance from appearing in the driver’s reference. Kelvin-source or Kelvin-emitter connections can separate the drive return from load current where the power package provides them.

Coordinate DESAT, Miller Clamp, and UVLO

Desaturation detection monitors on-state voltage through an external network in supported applications. Its threshold, blanking time, leading-edge filtering, diode behavior, fault latency, and soft-shutdown profile must fit the power switch. Too little blanking can create false trips during turn-on; too much can expose the device to excess short-circuit energy. For fast SiC systems, verify whether the recommended protection uses DESAT, shunt sensing, drain-source monitoring, or another method.

A Miller current flows through gate-drain or gate-collector capacitance when the opposite device changes voltage. If that current raises VGS above threshold, the nominally off switch can turn on. A Miller clamp provides a low-impedance path near the gate after turn-off. Negative gate bias is another tool, with its own isolated-supply and gate-limit tradeoffs.

TI’s Miller-clamp application brief explains how parasitic capacitance, dV/dt, gate impedance, unipolar/bipolar bias, and clamp placement affect false turn-on. An internal clamp reduces parts but must connect through the package and PCB; an external clamp can be placed close to a module gate. Calculate and measure the real loop.

Undervoltage lockout (UVLO) must keep the switch in a safe state while primary or secondary power rises or falls. Match thresholds and hysteresis to the power device’s gate requirements. Check what happens if only one side of the isolator is powered, if the isolated bias collapses during a fault, and whether the output is actively pulled low or becomes high impedance.

Include Isolated Bias, Layout, and Thermal Conditions

The secondary bias supply is part of the gate driver. Define positive and negative rails, regulation, startup, isolation rating/lifetime, primary-to-secondary capacitance, load transient, short-circuit response, and discharge. A small isolated converter with excessive coupling can inject common-mode current that undermines an otherwise capable driver.

Place local decoupling between the driver’s output-side supply and its return with the smallest loop. Route gate and return together, separate power-current and drive-current paths, and keep DESAT and fault networks away from the switch node. Follow creepage rules while also minimizing high-frequency loops; these goals need deliberate component placement rather than a generic “short traces” instruction.

Measure driver and bias temperatures in the production enclosure. Switching frequency, gate charge, Miller-clamp events, repeated faults, and ambient temperature contribute to loss. Repeated auto-retry into a short can overheat the driver, bias supply, gate resistor, or power device even when each individual pulse survives.

Qualify the Exact Driver With the Power Stage

Compare exact candidates by output rails, source/sink impedance, propagation delay/mismatch, CMTI conditions, minimum pulse, UVLO, default state, DESAT and soft shutdown, clamp architecture, fault reporting, reset, isolation certificates, package, creepage, temperature, and qualification. TI’s isolated gate-driver portfolio and Infineon families illustrate the breadth of configurations; a shared category is not a substitution claim.

Validate double-pulse switching, steady operation, minimum/maximum duty, startup/shutdown, dead time, load and bus extremes, high temperature, bias brownout, input fault, output short, and protection recovery. Observe both VGS at the device terminals and the switch voltage/current with measurement methods suited to high common mode.

For an alternate, re-run gate-resistor selection, timing, isolation, fault-energy, thermal, EMI, and layout review. Control driver and power-switch order codes, isolated-bias components, gate network, firmware timing, certificates, and test waveforms together. That evidence prevents a superficially compatible driver from changing the safety margin of the entire converter.