Hot-Swap Controller Selection: Inrush, MOSFET SOA, and Fault Timing

Table of Contents

• Define the Live-Insertion Event Before Selecting the Controller
• Turn Load Capacitance Into an Inrush Budget
• Select the MOSFET From Safe Operating Area
• Coordinate Current Limit, Circuit Breaker, and Timer
• Decide How the Rail Recovers
• Add Adjacent Protection Deliberately
• Test Insertion, Short Circuit, and Recovery

Hot-swap design is a controlled power event. When an uncharged board is inserted into a live connector, its input capacitors initially look like a low impedance. Without control, the resulting current can collapse the backplane, damage contacts, trip upstream protection, or overstress the board’s power switch.

A controller is approved only with its external MOSFET, sense element, timer, load capacitance, connector sequence, and recovery policy. The most common selection error is to size the MOSFET for steady-state resistance while ignoring the interval when it operates in its linear region.

Define the Live-Insertion Event Before Selecting the Controller

Document nominal, minimum, and maximum source voltage at the connector; source impedance; upstream current limit; connector pin sequencing; maximum load capacitance; downstream startup current; allowed voltage ramp; and the maximum disturbance the shared rail can tolerate. Include a partially charged load, a rapid re-insertion, and contact bounce where the mechanical system permits them.

Separate startup from fault requirements. Startup charges a known capacitance and then settles into normal load. An output short can hold the MOSFET at high voltage and current until a timer, circuit breaker, or thermal limit ends the event. The controller may use the same current-sense path for both, but the energy and recovery expectations are different.

The ADI hot-swap selection overview describes controllers as part of a complete circuit that limits inrush and protects a live supply. Use an original equipment manufacturer’s equations and design guidance for the chosen part; do not transfer a timer calculation between unrelated controller architectures.

Turn Load Capacitance Into an Inrush Budget

For a roughly linear voltage ramp, capacitor current is capacitance multiplied by the rate of voltage change. This gives a useful first estimate: a larger load capacitance, a faster ramp, or both require more current. Add the downstream circuit’s own startup demand, capacitor tolerance, voltage derating, and any staged rail enable.

Decide whether the design controls gate slew, enforces a current limit, or combines both. A pure gate-slew approach can make inrush sensitive to MOSFET capacitance and threshold variation. Current regulation gives a defined current but can hold the MOSFET in linear operation longer. The timer must allow the worst legitimate startup without permitting an unsafe fault pulse.

Check the source side as well. The hot-swap circuit cannot prevent an upstream rail from drooping if its selected inrush current exceeds the source’s transient capability. Coordinate downstream capacitance and ramp with any upstream eFuse or converter so their soft-start and fault timers do not fight each other.

Select the MOSFET From Safe Operating Area

Low RDS(on) reduces normal conduction loss, but startup can place the external MOSFET at substantial drain-to-source voltage while it carries the charging current. This is a linear-mode pulse. Verify the data-sheet safe operating area (SOA) at the relevant pulse duration and derate it for initial junction temperature, package, mounting, and repetition.

Estimate the MOSFET trajectory through voltage and current rather than checking a single endpoint. At the start of a constant-current charge, most input voltage may be across the MOSFET; as the output rises, VDS falls. A short circuit can hold VDS high until protection reacts. Some MOSFET data sheets provide only limited or typical linear-mode information, and modern low-resistance devices are not automatically robust in this region.

Also check VDS rating with surge margin, gate-voltage limits, threshold spread, RDS(on) at the controller’s available gate drive, drain-current and package limits, thermal impedance for the event duration, and body-diode orientation. Multiple parallel MOSFETs need a design that accounts for sharing in both conduction and linear operation; equal steady-state resistance does not guarantee equal transient stress.

Coordinate Current Limit, Circuit Breaker, and Timer

Controller families use different protection models. A current regulator may hold a defined limit. A circuit-breaker threshold may tolerate a brief overcurrent and then shut down. Foldback reduces current as output voltage collapses. A timer can integrate fault duration or start a fixed interval after a threshold is crossed.

Build a table for normal startup, load step, overload, hard short, input surge, and undervoltage. For each event, state the current threshold, allowed duration, gate action, status signal, and recovery. Include sense-resistor tolerance, threshold limits across temperature, filter delay, timer-capacitor tolerance, and MOSFET stress. A typical current-limit number is not enough to approve a worst-case SOA calculation.

TI’s hot-swap controller portfolio spans low- and high-voltage architectures with different protection functions. Microchip also separates controllers by application and feature set in its hot-swap product group. Compare exact data sheets; the category name does not promise foldback, telemetry, reverse blocking, or a particular timer model.

Decide How the Rail Recovers

Latch-off keeps the power switch off until enable, input power, or another defined reset changes state. It limits repeated stress but can leave an unattended system unavailable after a transient. Auto-retry attempts to restore service, yet the off-time must allow the MOSFET and surrounding board to cool before another pulse.

Some controllers retry indefinitely; others use a retry counter, progressively longer delays, or a controller-managed restart. Calculate worst-case repetitive power for a persistent short, including the possibility that ambient temperature is already high. Confirm what happens to power-good, fault, telemetry, and downstream reset signals throughout the cycle.

Define system ownership. If a management controller decides when to retry, it must remain powered and able to observe the fault. If reset requires physical removal, service documentation should say so. A robust circuit with an undefined operational reset path is still an incomplete design.

Add Adjacent Protection Deliberately

Hot-swap control, overvoltage protection, reverse-polarity protection, surge stopping, and ideal-diode ORing are related but distinct. Some ICs combine several functions; others expect separate blocks. Draw the power path and assign responsibility for every state before selecting a highly integrated device.

An ideal-diode controller primarily manages forward drop and reverse current or ORing. It may share an external MOSFET topology with hot-swap protection without sharing the same current-limit or startup behavior. Similarly, an eFuse often integrates a switch and may be a better fit at lower energy, while an external-MOSFET controller gives the designer more freedom to size SOA and conduction loss.

Check undervoltage and overvoltage thresholds with resistor tolerance, hysteresis, leakage, and sequencing. If the circuit must ride through a specified surge rather than shut down, the controller/MOSFET thermal trajectory needs a surge-stopper analysis, not a simple absolute-maximum comparison.

Test Insertion, Short Circuit, and Recovery

Use the production connector, source impedance, input cable, load capacitance, MOSFET, layout, and airflow. Record input voltage, output voltage, input current, gate voltage, MOSFET VDS, fault/status outputs, and relevant temperatures. Test cold start, hot insertion, bounce, rapid reinsertion, partially charged output, maximum capacitance, and minimum input.

Apply overloads and shorts at startup and after the rail is established. Verify timer action, foldback, shutdown, discharge, latch or retry, and upstream-rail disturbance. Repeat enough cycles to expose accumulating heat. Confirm that the measurement setup does not add inductance or probe grounding that changes the event.

For an alternate, require the same calculations and waveforms with its exact controller and MOSFET. Pin compatibility does not prove matching gate drive, thresholds, timer law, status outputs, or SOA protection. Store the approved component codes, operating envelope, test conditions, and recovery policy together so a future supply substitution does not silently change how the system handles live power.